Future-proofing your smart meter design
Posted by: Metering.com
August 18, 2008
By Kerry Glover
The power meter industry is undergoing a significant change in systems requirements. With the first wave of smart meters having been deployed, we are faced with many continually changing requirements. This presents power meter designers with the growing problem of developing a meter that will meet the requirements not only for today but also for the next 10 to 20 years.
In many cases, a new smart meter will be installed with a major rollout of millions of units per year with a total infrastructure cost in the billions. These are no longer simple metrology measurement devices but full-blown computer systems with network communications capabilities which are expected to operate without being replaced for the next 10 to 20 years. How many people are still using the computer they bought 10 years ago? It is easy to run out of performance over this period of time as requirement change and standardisation is required.
Traditional simple digital power meters did not need to be so smart. They could be easily run with a slow, low cost microprocessor. However, to provide for the most cost effective and reliable solutions, these 8-bit microprocessors were each integrated into a system-on-chip (SOC) with the analogue to digital converter (ADC) and other optimised peripherals such as LCD, watchdog timers (WDT) and realtime clock (RTC). This provided very good, cost optimised solutions for first generation digital meters.
However, the need to have compatibility among all of the meters in a metropolitan area or in a country is leading to the requirements for more standardisation, using specifications such as DLMS or C12.19. These standards have a lot of flexibility and overhead designed into them, which requires a significantly increased amount of processing power. In these cases, the traditional 8-bit microprocessor does not have enough capabilities. In many cases, designers are adding a second microprocessor to handle the database and communication protocol. In order to future-proof the design and with the minimal cost delta, many designers are moving to 32-bit processors.
The problem now is that the systems cost can get out of hand. Why pay for multiple processors when a single processor is adequate? This has led to the use of a metrology front-end, such as the CS5463 from Cirrus Logic Inc., with a 32-bit microprocessor to minimise cost. However, this is still not as cost effective since one loses the optimised peripheral set provided by the SOC. There needs to be a better way!
Introducing the CS7401xx architecture
Cirrus Logic’s new CS7401xx series of 32-bit SOCs solves many of these problems. This product leverages the company’s long history of leadership in ADC and metrology capabilities with an innovative approach to overall integration and high performance. With the introduction of the CS7401xx, Cirrus Logic’s product line now covers the entire range of solutions needed, from basic ADC-based metrology only all the way to the new smart meters and beyond.
An additional benefit of the SOC approach is the amount of software support provided by Cirrus Logic Inc. An extensive library of support routine and sample application allows for rapid application development. Many of the basic metrology functions are included in the 32 kB of ROM code, reducing the final footprint of the application in the Flash memory and reducing the devel-opment effort. This development in a C-based, 32-bit architecture with precision ADCs, plenty of compute power, hardware 32×32 multiplier and optimised peripherals is a dream come true.
The heart of the precision metrology SOC is three high precision Delta-Sigma ADCs. These can be configured to run at speeds of 1 kHz, 2 kHz, 4 kHz or 8 kHz. This allows the user to configure the amount of accuracy and power consumption they want for their system. Multiple ADC allows for accurate sampling of voltage and current at the same time with a third ADC available for theft detection.
Another changing requirement facing designers is the measurement of non-linear power consumption. This traditionally has been with poor power factor. However, with the advent of modern switched mode regulators, harmonic frequency content must also be measured. This requires high sampling rates to get up to the 20 or even 40 harmonics. If this becomes the standard in the next 10 years, the CS7401xx device will be capable of providing the measurements.
The compute power is provided by 32-bit ARM® TDMITM CPU. This includes an embedded multiplier for fast signal processing. This processor can be configured dynamically to provide from 4 MHz to 32 MHz operation. This is coupled with up to 128 kB of on-chip Flash memory and 8 kB of RAM to provide the needed compute resources and code space. The optimised peripherals include LCD, RTC, WDT, timers, SPI, UART, E-Pulse and GPIO interfaces.
The ROM code contains metrology algorithms that allow very accurate measurements of not only the active and reactive power but also the fundamental and harmonic power. A special algorithm allows for very accurate fundamental reactive power measurement which can be used to help with power factor correction. Measurement of poor power factor or high harmonic content is the first step in getting feedback to the consumer such that he can change is consumption patterns.
The metrology calculations typically consume less than 4 MHz of bandwidth allowing operation most of the time in the 4 MHz mode. However, when more power is needed, this can be increased to 32 MHz. An example might be the system running for normal operation at 4 MHz until an interrupt comes from a communications interface. The processor can then change the clock speed to 32 MHz, handle all of the communication protocols, and then go back to the 4 MHz operation low power mode.
Another key benefit of this architecture is the ability to override this ROM-based metrology code with custom Flash-based code. While the ROM-based metrology is expected to handle all near term needs, future requirements may require special functionality. If this future code needs more computing power, the clock speed can be increased at that time to handle these advanced needs. One example might be the measurement of each harmonic. If future standards require the inclusion of this feature, the CS7401 can provide the capabilities.
With the cost of energy increasing dramatically, there is much more demand on the ability for consumers to control their electricity consumption. However, consumers have little or no visibility into how to change their behaviour to reduce electricity consumption except for the once a month feedback in the form of an electricity bill. By simply giving consumers access to this information, their consumption patterns will change.
Having more processing resources (MIPS, Flash program store and RAM) allows for advanced database management capabilities inside the meter. Having the right peripheral mix including a real time clock allows for the smart meter to store time-of-use (TOU) information along with the energy usage information. Having the right communication resources allows the transfer of this information into the house to the consumer. Having all of this capability in a single SOC makes all of this economically feasible.
With the introduction of the CS7401xx series, in conjunction with its proven families of ADC products already used widely for energy metering systems throughout the world, Cirrus Logic is now one of the few semiconductor companies that can provide solutions from the low end to the high end of meter design requirements. The CS7401xx series offers the benefit of significant savings on development cost by having a single, unified architecture across all product lines, along with the ability to smoothly and cost effectively evolve product offerings to accommodate future requirements.
As energy management requirements continue to evolve with the needs for both cost reduction on the part of utilities and for enhanced global energy conservation efforts, chip level building blocks such as the Cirrus Logic CS7401xx series will provide the underlying basis of performance, functionality and forward flexibility needed to meet these challenges.